Phase locked loops are used in a wide range of applications such as clock generation, clock alignment, deskewing, jitter reduction, clock distribution, frequency synthesis, etc. Communication systems often include multiple cards such as timing cards and line cards that are connected together by a backplane bus. Each timing card and line card typically includes at least one Phase Locked Loop (PLL) timing device.
It is difficult for vendors of PLL timing devices to demonstrate that their PLL timing devices will work well in systems that include multiple PLL timing devices such as systems that include timing cards and line cards. Product demonstration for these systems is usually performed using an evaluation board that only includes a single timing device. Though it is sometimes possible to connect the single PLL timing device to the customer's communication system to allow the customer to evaluate the operation of the PLL timing device in the customer's system, the process of connecting the evaluation board to the customer's system is difficult and time consuming. Often it is not even possible, depending on the characteristics of the customer's system.
Even if connection to the customer's system is achieved, connecting an evaluation board having a single PLL timing device does not allow for evaluation of complex systems that include multiple PLL timing devices. Furthermore, to evaluate the effect of using different PLL-timed physical devices such as different Ethernet PLL-timed physical devices requires the use of a customer system that includes the different Ethernet PLL-timed physical device. Accordingly there is a need for a method and apparatus that will allow for the evaluation of multi-card communication systems that include more than one PLL timing device.